/**
 * @file
 * @brief SOC描述层：GPIO
 * @author
 * + 隐星魂 (Roy Sun) <xwos@xwos.tech>
 * @copyright
 * + Copyright © 2015 xwos.tech, All Rights Reserved.
 * > Licensed under the Apache License, Version 2.0 (the "License");
 * > you may not use this file except in compliance with the License.
 * > You may obtain a copy of the License at
 * >
 * >         http://www.apache.org/licenses/LICENSE-2.0
 * >
 * > Unless required by applicable law or agreed to in writing, software
 * > distributed under the License is distributed on an "AS IS" BASIS,
 * > WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * > See the License for the specific language governing permissions and
 * > limitations under the License.
 */

#ifndef __xwcd_soc_arm_v8a_a72_bcm2711_soc_gpio_h__
#define __xwcd_soc_arm_v8a_a72_bcm2711_soc_gpio_h__

#include <xwos/standard.h>
#include <xwcd/soc/arm64/v8a/a72/bcm2711/soc.h>

struct soc_gpio_regs {
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel0:3;
                        xwu32_t fsel1:3;
                        xwu32_t fsel2:3;
                        xwu32_t fsel3:3;
                        xwu32_t fsel4:3;
                        xwu32_t fsel5:3;
                        xwu32_t fsel6:3;
                        xwu32_t fsel7:3;
                        xwu32_t fsel8:3;
                        xwu32_t fsel9:3;
                        xwu32_t reserved0:2;
                } bit;
        } gpfsel0; /**< 0x00 GPIO Function Select 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel10:3;
                        xwu32_t fsel11:3;
                        xwu32_t fsel12:3;
                        xwu32_t fsel13:3;
                        xwu32_t fsel14:3;
                        xwu32_t fsel15:3;
                        xwu32_t fsel16:3;
                        xwu32_t fsel17:3;
                        xwu32_t fsel18:3;
                        xwu32_t fsel19:3;
                        xwu32_t reserved0:2;
                } bit;
        } gpfsel1; /**< 0x04 GPIO Function Select 1 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel20:3;
                        xwu32_t fsel21:3;
                        xwu32_t fsel22:3;
                        xwu32_t fsel23:3;
                        xwu32_t fsel24:3;
                        xwu32_t fsel25:3;
                        xwu32_t fsel26:3;
                        xwu32_t fsel27:3;
                        xwu32_t fsel28:3;
                        xwu32_t fsel29:3;
                        xwu32_t reserved0:2;
                } bit;
        } gpfsel2; /**< 0x08 GPIO Function Select 2 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel30:3;
                        xwu32_t fsel31:3;
                        xwu32_t fsel32:3;
                        xwu32_t fsel33:3;
                        xwu32_t fsel34:3;
                        xwu32_t fsel35:3;
                        xwu32_t fsel36:3;
                        xwu32_t fsel37:3;
                        xwu32_t fsel38:3;
                        xwu32_t fsel39:3;
                        xwu32_t reserved0:2;
                } bit;
        } gpfsel3; /**< 0x0C GPIO Function Select 3 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel40:3;
                        xwu32_t fsel41:3;
                        xwu32_t fsel42:3;
                        xwu32_t fsel43:3;
                        xwu32_t fsel44:3;
                        xwu32_t fsel45:3;
                        xwu32_t fsel46:3;
                        xwu32_t fsel47:3;
                        xwu32_t fsel48:3;
                        xwu32_t fsel49:3;
                        xwu32_t reserved0:2;
                } bit;
        } gpfsel4; /**< 0x10 GPIO Function Select 4 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t fsel50:3;
                        xwu32_t fsel51:3;
                        xwu32_t fsel52:3;
                        xwu32_t fsel53:3;
                        xwu32_t fsel54:3;
                        xwu32_t fsel55:3;
                        xwu32_t fsel56:3;
                        xwu32_t fsel57:3;
                        xwu32_t reserved0:8;
                } bit;
        } gpfsel5; /**< 0x14 GPIO Function Select 5 */
        xwu32_t reserved0; /**< 0x18 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpset0; /**< 0x1C GPIO Pin Output Set 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpset1; /**< 0x20 GPIO Pin Output Set 1 */
        xwu32_t reserved1; /**< 0x24 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpclr0; /**< 0x28 GPIO Pin Output Clear 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpclr1; /**< 0x2C GPIO Pin Output Clear 1 */
        xwu32_t reserved2; /**< 0x30 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gplev0; /**< 0x34 GPIO Pin Level 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gplev1; /**< 0x38 GPIO Pin Level 1 */
        xwu32_t reserved3; /**< 0x3C */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpeds0; /**< 0x40 GPIO Pin Event Detect Status 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpeds1; /**< 0x44 GPIO Pin Event Detect Status 1 */
        xwu32_t reserved4; /**< 0x48 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpren0; /**< 0x4C GPIO Pin Rising Edge Detect Enable 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpren1; /**< 0x50 GPIO Pin Rising Edge Detect Enable 1 */
        xwu32_t reserved5; /**< 0x54 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpfen0; /**< 0x58 GPIO Pin Falling Edge Detect Enable 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpfen1; /**< 0x5C GPIO Pin Falling Edge Detect Enable 1 */
        xwu32_t reserved6; /**< 0x60 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gphen0; /**< 0x64 GPIO Pin High Detect Enable 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gphen1; /**< 0x68 GPIO Pin High Detect Enable 1 */
        xwu32_t reserved7; /**< 0x6C */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gplen0; /**< 0x70 GPIO Pin Low Detect Enable 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gplen1; /**< 0x74 GPIO Pin Low Detect Enable 1 */
        xwu32_t reserved8; /**< 0x78 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gparen0; /**< 0x7C GPIO Pin Async. Rising Edge Detect 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gparen1; /**< 0x80 GPIO Pin Async. Rising Edge Detect 1 */
        xwu32_t reserved9; /**< 0x84 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:1;
                        xwu32_t pin1:1;
                        xwu32_t pin2:1;
                        xwu32_t pin3:1;
                        xwu32_t pin4:1;
                        xwu32_t pin5:1;
                        xwu32_t pin6:1;
                        xwu32_t pin7:1;
                        xwu32_t pin8:1;
                        xwu32_t pin9:1;
                        xwu32_t pin10:1;
                        xwu32_t pin11:1;
                        xwu32_t pin12:1;
                        xwu32_t pin13:1;
                        xwu32_t pin14:1;
                        xwu32_t pin15:1;
                        xwu32_t pin16:1;
                        xwu32_t pin17:1;
                        xwu32_t pin18:1;
                        xwu32_t pin19:1;
                        xwu32_t pin20:1;
                        xwu32_t pin21:1;
                        xwu32_t pin22:1;
                        xwu32_t pin23:1;
                        xwu32_t pin24:1;
                        xwu32_t pin25:1;
                        xwu32_t pin26:1;
                        xwu32_t pin27:1;
                        xwu32_t pin28:1;
                        xwu32_t pin29:1;
                        xwu32_t pin30:1;
                        xwu32_t pin31:1;
                } bit;
        } gpafen0; /**< 0x88 GPIO Pin Async. Falling Edge Detect 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:1;
                        xwu32_t pin33:1;
                        xwu32_t pin34:1;
                        xwu32_t pin35:1;
                        xwu32_t pin36:1;
                        xwu32_t pin37:1;
                        xwu32_t pin38:1;
                        xwu32_t pin39:1;
                        xwu32_t pin40:1;
                        xwu32_t pin41:1;
                        xwu32_t pin42:1;
                        xwu32_t pin43:1;
                        xwu32_t pin44:1;
                        xwu32_t pin45:1;
                        xwu32_t pin46:1;
                        xwu32_t pin47:1;
                        xwu32_t pin48:1;
                        xwu32_t pin49:1;
                        xwu32_t pin50:1;
                        xwu32_t pin51:1;
                        xwu32_t pin52:1;
                        xwu32_t pin53:1;
                        xwu32_t pin54:1;
                        xwu32_t pin55:1;
                        xwu32_t pin56:1;
                        xwu32_t pin57:1;
                        xwu32_t reserved0:8;
                } bit;
        } gpafen1; /**< 0x8C GPIO Pin Async. Falling Edge Detect 1 */
        xwu32_t reserved10[21]; /**< 0x90 ~ 0xE0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin0:2;
                        xwu32_t pin1:2;
                        xwu32_t pin2:2;
                        xwu32_t pin3:2;
                        xwu32_t pin4:2;
                        xwu32_t pin5:2;
                        xwu32_t pin6:2;
                        xwu32_t pin7:2;
                        xwu32_t pin8:2;
                        xwu32_t pin9:2;
                        xwu32_t pin10:2;
                        xwu32_t pin11:2;
                        xwu32_t pin12:2;
                        xwu32_t pin13:2;
                        xwu32_t pin14:2;
                        xwu32_t pin15:2;
                } bit;
        } gpio_pup_pdn_cntrl_reg0; /**< 0xE4 GPIO Pull-up / Pull-down Register 0 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin16:2;
                        xwu32_t pin17:2;
                        xwu32_t pin18:2;
                        xwu32_t pin19:2;
                        xwu32_t pin20:2;
                        xwu32_t pin21:2;
                        xwu32_t pin22:2;
                        xwu32_t pin23:2;
                        xwu32_t pin24:2;
                        xwu32_t pin25:2;
                        xwu32_t pin26:2;
                        xwu32_t pin27:2;
                        xwu32_t pin28:2;
                        xwu32_t pin29:2;
                        xwu32_t pin30:2;
                        xwu32_t pin31:2;
                } bit;
        } gpio_pup_pdn_cntrl_reg1; /**< 0xE8 GPIO Pull-up / Pull-down Register 1 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin32:2;
                        xwu32_t pin33:2;
                        xwu32_t pin34:2;
                        xwu32_t pin35:2;
                        xwu32_t pin36:2;
                        xwu32_t pin37:2;
                        xwu32_t pin38:2;
                        xwu32_t pin39:2;
                        xwu32_t pin40:2;
                        xwu32_t pin41:2;
                        xwu32_t pin42:2;
                        xwu32_t pin43:2;
                        xwu32_t pin44:2;
                        xwu32_t pin45:2;
                        xwu32_t pin46:2;
                        xwu32_t pin47:2;
                } bit;
        } gpio_pup_pdn_cntrl_reg2; /**< 0xEC GPIO Pull-up / Pull-down Register 2 */
        union {
                xwu32_t u32;
                struct {
                        xwu32_t pin48:2;
                        xwu32_t pin49:2;
                        xwu32_t pin50:2;
                        xwu32_t pin51:2;
                        xwu32_t pin52:2;
                        xwu32_t pin53:2;
                        xwu32_t pin54:2;
                        xwu32_t pin55:2;
                        xwu32_t pin56:2;
                        xwu32_t pin57:2;
                        xwu32_t reserved0:12;
                } bit;
        } gpio_pup_pdn_cntrl_reg3; /**< 0xF0 GPIO Pull-up / Pull-down Register 3 */
};

#define soc_gpio (*((volatile struct soc_gpio_regs *)SOC_GPIO_REGBASE))

#define SOC_GPIO_ALT_GPI                0U
#define SOC_GPIO_ALT_GPO                1U
#define SOC_GPIO_ALT5                   2U
#define SOC_GPIO_ALT4                   3U
#define SOC_GPIO_ALT0                   4U
#define SOC_GPIO_ALT1                   5U
#define SOC_GPIO_ALT2                   6U
#define SOC_GPIO_ALT3                   7U

#define SOC_GPIO_PUPDC_NO               0U
#define SOC_GPIO_PUPDC_PU               1U
#define SOC_GPIO_PUPDC_PD               2U

#endif /* xwcd/soc/arm64/v8a/a72/bcm2711/soc_gpio.h */
